Extended length counter chains in FPGA logic

ABSTRACT

A synchronous counter, the inventive counter is synchronized to a clock, e.g., a master clock of an FPGA, and includes a first counter that increments in response to the master clock, a resynchronizer that receives counter bits from the first counter and, when appropriate, generates an increment signal, and a second counter, clocked by the master clock, that increments in response to the increment signal. In a preferred embodiment, the resynchronizer is an n bit AND gate (where the first counter is an n-bit counter) that ANDs at least selected ones of the counter bits and a latch, e.g., a flip-flop, that latches the output of the AND gate. Thus, small counter chains are linked together using flip-flops clocked at the master clock rate, i.e., the same rate as the counter chains, to form a counter chain of any length that will function at the master clock rate. Accordingly, counter chains of unlimited size that can be implemented in a field programmable logic array (FPGA) and that can run at the maximum clock rate of the FPGA can be realized.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to gate array logic. Morespecifically, the present invention relates to counter chains that maybe implemented in field programmable gate array logic.

[0003] 2. Description of the Related Art

[0004] The maximum length of prior art counter chains was limited by thecarry-forward ripple delay through the chain. Typical field programmablelogic arrays (FPGAs) include variable length counter chains with aserial carry look-ahead output. These variable length counter chains arelinked together with the carry look-ahead output of one counter chainstage being passed to a carry input of the next counter chain stage.When the individual stage delay, as multiplied by the number of stagesin a counter, exceeded the period between clocks, the counter would nolonger count correctly. Further, even if these counters include fastlook-ahead logic, there remains the fundamental counter chain lengthlimitation that the overall carry delay, increased by each stage, mustnot exceed the clock period. So, for example, on a typical currentlyavailable FPGA, the longest counter chain supported with a basic clockrate of 80 Megahertz, the maximum number of counter stages is about 17or 18 stages.

[0005] Accordingly, there is a need for counter chains that may be ofany length without regard to the carry-forward ripple delay.

SUMMARY OF THE INVENTION

[0006] The present invention is a synchronous counter synchronized to amaster clock. The master clock may be a clock on an FPGA chip. Thecounter includes a first counter that increments in response to themaster clock. A resynchronizer receives counter bits from the firstcounter and, when appropriate, generates an increment signal. A secondcounter, clocked by the master clock, increments in response to theincrement signal. The resynchronizer is an n bit AND gate (where thefirst counter is an n-bit counter) that ANDs at least selected ones ofthe counter bits of the first counter, and a latch clocked by the masterclock for latching the output of the AND gate. Thus, small counterchains are linked together using flip-flops clocked at the master clockrate, i.e., the same rate as the counter chains, to form a counter chainof any length that will function at the master clock rate. Accordingly,the present invention encompasses counter chains of unlimited size thatcan be implemented in a field programmable logic array (FPGA) and thatcan run at the maximum clock rate of the FPGA.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The sole FIGURE depicts a counter including a look aheadresynchronizing stage according to a preferred embodiment of the presentinvention.

DESCRIPTION OF THE INVENTION

[0008] Illustrative embodiments and exemplary applications will now bedescribed with reference to the accompanying drawings to disclose theadvantageous teachings of the present invention.

[0009] While the present invention is described herein with reference toillustrative embodiments for particular applications, it should beunderstood that the invention is not limited thereto. Those havingordinary skill in the art and access to the teachings provided hereinwill recognize additional modifications, applications, and embodimentswithin the scope thereof and additional fields in which the presentinvention would be of significant utility.

[0010] The sole FIGURE depicts a counter including a look aheadresynchronizing stage according to a preferred embodiment of the presentinvention. In this example, two small n bit counter chains 100, 102 arelinked together by a resynchronizing stage that includes a flip-flop 104and an AND gate 106. The n bit counter chains count from 0 to N-1, whereN=2^(n).

[0011] Flip-flop 104 is clocked at the same rate as the counter chains,i.e. at the master clock rate. AND gate 106 (or a circuit providing anequivalent function) ANDs all but the least significant of the n counterbits and passes the result to the data input of flip-flop 104. Theoutput 108 of flip-flop 104 is passed to the enable input of second nbit counter 102. Although counters 100, 102 are shown in this example tobe identical n bit counters, this is by way of example only and notintended as a limitation. Also, although the exemplary embodimentincludes two counters 100, 102 synchronized by a resynchronizer, anynumber of counters may be linked using a resynchronizer between linkedpairs without departing from the spirit or scope of the invention.

[0012] Essentially, the resynchronizer stage captures the output of thefirst n bit counter 100 when it reaches the count of 2^(n)-2, i.e., onecount state before the normal rollover point of 2^(n)-1. Thus, byclocking a resynchronizing flip-flop at this point, the counter carrystring is anticipated and the flip-flop output 108 is synchronized tothe main clock 110. The flip-flop output 108 enables the second n bitcounter 102 for a single clock period. During that clock period, thesecond n bit counter is incremented once and disabled in the next clockperiod, when the clock 112 resets flip-flop 104. Thus, the entirecounter chain counts normally, even though the carry delay for the n bitcounters may exceed the clock period.

[0013] For comparison, a prior art counter and a counter according tothe preferred embodiment of the present invention were implemented on acommercially available FPGA chip, a Flex 8000 chip from Altera. Thefastest prior art counter was limited to 32 stages at a maximum chipclock rate of 20 MHz. However, the 32 bit counter of the presentinvention exhibited no failures with the chip clock speed extended to 80MHz

[0014] Accordingly, the present invention is applicable to all counterdesigns for FPGA's or similar devices that incorporate long counterstrings. The present invention allows the use of cheaper and slowerdevices than could otherwise be used with a ripple carry type counter.

[0015] Thus, the present invention has been described herein withreference to a particular embodiment for a particular application. Thosehaving ordinary skill in the art and access to the present teachingswill recognize additional modifications, applications and embodimentswithin the scope thereof.

[0016] It is therefore intended by the appended claims to cover any andall such applications, modifications and embodiments within the scope ofthe present invention.

[0017] Accordingly,

What is claimed is:
 1. A synchronous counter comprising: a first counterfor receiving a clock signal and incrementing a first counter inresponse thereto; a resynchronizer for receiving counter bits from thefirst counter and generating an increment signal in response thereto;and a second counter for incrementing a second count in response to theincrement signal and the clock signal.
 2. A synchronous counter as inclaim 1 wherein the resynchronizer comprises: an AND gate that ANDs atleast selected ones of the counter bits and a latch that latches aresult from the AND gate.
 3. A synchronous counter as in claim 2 whereinthe first counter is an n bit counter and the AND gate ANDs the n mostsignificant counter bits.
 4. A synchronous counter as in claim 3 whereinan output of the latch is coupled to an enable input of the secondcounter.
 5. A synchronous counter as in claim 4 wherein the secondcounter is an n bit counter.
 6. A synchronous counter as in claim 5wherein the carry propagation delay through the first counter exceedsthe period of the clock.
 7. A synchronous counter as in claim 6 whereinthe synchronous counter is a counter of a field programmable gate array(FPGA) and the clock is a master clock for the FPGA.
 8. A synchronouscounter as in claim 1 wherein the resynchronizer comprises: a logic gatethat logically combines at least selected ones of the counter bits andproduces an output representative of the result and a latch that latchesthe output of the logic gate.
 9. A synchronous counter as in claim 8wherein the latch comprises a flip-flop.
 10. A synchronous counter as inclaim 8 wherein the logic gate comprises an AND gate.
 11. A synchronouscounter as in claim 9 wherein the logic gate comprises an AND gate. 12.A synchronous counter comprising: first counting means for incrementingin response to a clock, wherein a carry propagation delay through thefirst counting means exceeds the period of the clock; resynchronizingmeans for anticipating a carry from the first counting means and forgenerating an increment signal responsive to the anticipated carry andthe clock; and second counting means for incrementing in response to theincrement signal and the master clock.
 13. A synchronous counter as inclaim 12 wherein the means for resynchronizing comprises: means forcombining at least selected counter bits from the first counting meansand for producing a result prior to the occurrence of a carry; and meansfor latching the result.
 14. A synchronous counter as in claim 13wherein the first counting means is an n-bit counter, and the combiningmeans combines the n most significant counter bits to produce theresult.
 15. A synchronous counter as in claim 14 wherein the incrementsignal is the result.
 16. A synchronous counter as in claim 15 whereinthe second counting means is an n-bit counter.
 17. A synchronous counteras in claim 12 wherein the carry propagation delay through the firstcounting means exceeds the period of the clock.
 18. A synchronouscounter as in claim 12 wherein the synchronous counter is a counter of afield programmable gate array (FPGA) and the clock is a master clock forthe FPGA.
 19. A synchronous counter as in claim 12 wherein theresynchronizing means comprises: a logic gate that logically combines atleast selected ones of the counter bits and produces an outputrepresentative of the result; and a latch that latches the output of thelogic gate.
 20. A synchronous counter as in claim 19 wherein the latchcomprises a flip-flop. gate.